多路选择器
module mux2_1
(
input wire in_1,
input wire in_2,
input wire sel ,
output reg out
);
always@(*)
if(sel == 1'b1)
out = in_1;
else
out = in_2;
endmodule三八译码器
module decoder
(
input wire in_1,
input wire in_2,
input wire in_3,
output reg [7:0] out
);
/*
always@(*)
if({in_1,in_2,in_3} ==3'b000)
out = 8'b0000_0001;
else if({in_1,in_2,in_3} ==3'b001)
out = 8'b0000_0010;
else if({in_1,in_2,in_3} ==3'b010)
out = 8'b0000_0100;
else if({in_1,in_2,in_3} ==3'b011)
out = 8'b0000_1000;
else if({in_1,in_2,in_3} ==3'b100)
out = 8'b0001_0000;
else if({in_1,in_2,in_3} ==3'b101)
out = 8'b0010_0000;
else if({in_1,in_2,in_3} ==3'b110)
out = 8'b0100_0000;
else if({in_1,in_2,in_3} ==3'b111)
out = 8'b1000_0000;
else
out = 8'b0000_0000;
*/
always@(*)
case({in_1,in_2,in_3})
3'b000:out = 8'b0000_0001;
3'b001:out = 8'b0000_0010;
3'b010:out = 8'b0000_0100;
3'b011:out = 8'b0000_1000;
3'b100:out = 8'b0001_0000;
3'b101:out = 8'b0010_0000;
3'b110:out = 8'b0100_0000;
3'b111:out = 8'b1000_0000;
default:out = 8'b0000_0000;
endcase
endmodule半加器
module half_adder
(
input wire in_1,
input wire in_2,
output wire sum,
output wire count
);
assign {count,sum} = in_1 + in_2;
endmodule全加器
module full_adder
(
input wire in_1,
input wire in_2,
input wire cin,
output wire sum,
output wire count
);
wire h0_sum;
wire h0_count;
wire h1_count;
half_adder half_adder_inst0
(
.in_1(in_1),
.in_2(in_2),
.sum(h0_sum),
.count(h0_count)
);
half_adder half_adder_inst1
(
.in_1(cin),
.in_2(h0_sum),
.sum(sum),
.count(h1_count)
);
assign count = (h0_count|h1_count);
endmodule寄存器
module flip_flop
(
input wire sys_clk,
input wire sys_rst_n,
input wire key_in,
output reg led_out
);
always@(posedge sys_clk )//or negedge sys_rst_n
if(sys_rst_n == 1'b0)
led_out <= 1'b0;
else
led_out <= key_in;
endmodule计数器
module counter
#(
parameter CNT_MAX = 25'd24_999_999
)
(
input wire sys_clk ,
input wire sys_rst_n,
output reg led_out
);
reg [24:0] cnt;
reg cnt_flaf;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt <= 25'd0;
else if(cnt ==CNT_MAX )
cnt <= 25'd0;
else
cnt <= cnt + 25'd1;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_flaf <= 1'b0;
else if(cnt == (CNT_MAX-25'd1))
cnt_flaf <= 1'b1;
else
cnt_flaf <= 1'b0;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
led_out <= 1'b0;
else if(cnt_flaf ==1'b1 )
led_out <= ~led_out;
else
led_out <= led_out;
endmodule奇分频
module divider_five
(
input wire sys_clk ,
input wire sys_rst_n,
output reg clk_flag
);
reg [2:0] cnt;
/* reg clk_1;
reg clk_2; */
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt <= 3'd0;
else if(cnt ==3'd4)
cnt <= 3'd0;
else
cnt <= cnt + 3'd1;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
clk_flag <=1'b0;
else if(cnt == 3'd3)
clk_flag <= 1'b1;
else
clk_flag <= 0;
/* always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
clk_1 <= 1'b0;
else if(cnt == 3'd2)
clk_1 <=1'b1;
else if(cnt == 3'd4)
clk_1 <=1'b0;
else
clk_1 <= clk_1;
always@(negedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
clk_2 <= 1'b0;
else if(cnt == 3'd2)
clk_2 <=1'b1;
else if(cnt == 3'd4)
clk_2 <=1'b0;
else
clk_2 <= clk_2;
assign clk_out = (clk_1 | clk_2); */
endmodule偶分频
module divider_six
(
input wire sys_clk,
input wire sys_rst_n,
output reg clk_flag
/* output reg clk_out */
);
reg [2:0] cnt;
/* always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt <= 2'd0;
else if(cnt == 2'd2)
cnt <= 2'd0;
else
cnt <= cnt + 2'd1;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
clk_out <=1'b0;
else if(cnt == 2'd2)
clk_out <= ~clk_out;
else
clk_out <= clk_out; */
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt <= 3'd0;
else if(cnt == 3'd5)
cnt <= 3'd0;
else
cnt <= cnt + 3'd1;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
clk_flag <= 1'b0;
else if(cnt == 3'd4)
clk_flag <= 1'b1;
else
clk_flag <= 1'b0;
endmodule按键消抖
module key_filter
#(
parameter CNT_MAX = 20'd999_999
)
(
input wire sys_clk ,
input wire sys_rst_n,
input wire key_in,
output reg key_flag
);
reg [19:0] cnt_20ms;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_20ms <= 20'd0;
else if(key_in == 1'b1)
cnt_20ms <= 20'd0;
else if(key_in == CNT_MAX)
cnt_20ms <= CNT_MAX;
else
cnt_20ms <= cnt_20ms + 20'd1;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
key_flag <= 1'b0;
else if(cnt_20ms == (CNT_MAX - 20'd1))
key_flag <= 1'b1;
else
key_flag <= 1'b0;
endmodule呼吸灯
module bVerilogreath_led
#(
parameter CNT_1US_MAX = 6'd49 ,
parameter CNT_1MS_MAX = 10'd999,
parameter CNT_1S_MAX = 10'd999
)
(
input wire sys_clk ,
input wire sys_rst_n,
output reg led_out
);
reg [9:0] cnt_1s;
reg [9:0] cnt_1ms;
reg [5:0] cnt_1us;
reg cnt_en;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_1us <= 6'd0;
else if(cnt_1us == CNT_1US_MAX)
cnt_1us <= 6'd0;
else
cnt_1us <= cnt_1us + 6'd1;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_1ms <= 10'd0;
else if((cnt_1ms == CNT_1MS_MAX)&&(cnt_1us == CNT_1US_MAX))
cnt_1ms <= 10'd0;
else if(cnt_1us == CNT_1US_MAX)
cnt_1ms <= cnt_1ms + 10'd1;
else
cnt_1ms <= cnt_1ms;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_1s <= 10'd0;
else if((cnt_1s == CNT_1S_MAX)&&(cnt_1ms == CNT_1MS_MAX)&&(cnt_1us == CNT_1US_MAX))
cnt_1s <= 10'd0;
else if((cnt_1ms == CNT_1MS_MAX)&&(cnt_1us == CNT_1US_MAX))
cnt_1s <= cnt_1s + 10'd1;
else
cnt_1s <= cnt_1s;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_en <= 1'b0;
else if((cnt_1s == CNT_1S_MAX)&&(cnt_1ms == CNT_1MS_MAX)&&(cnt_1us == CNT_1US_MAX))
cnt_en <= ~cnt_en;
else
cnt_en <= cnt_en;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
led_out <= 1'b1;
else if(((cnt_en == 1'b0)&&(cnt_1ms <= cnt_1s))||((cnt_en == 1'b1)&&(cnt_1ms > cnt_1s)))
led_out <= 1'b0;
else
led_out <= 1'b1;
endmodule状态机
module complex_fsm
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire pi_money_half,
input wire pi_money_one,
output reg po_cola ,
output reg po_money
);
parameter IDLE = 5'b00001,
HALF = 5'b00010,
ONE = 5'b00100,
ONE_HALF = 5'b01000,
TWO = 5'b10000;
wire [1:0] pi_money;
reg [4:0] state;
assign pi_money = {pi_money_one,pi_money_half};
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
state <= IDLE;
else case(state)
IDLE : if(pi_money ==2'b01)
state <= HALF;
else if(pi_money == 2'b10)
state <= ONE;
else
state <= IDLE;
HALF : if(pi_money ==2'b01)
state <= ONE;
else if(pi_money == 2'b10)
state <= ONE_HALF;
else
state <= HALF;
ONE : if(pi_money ==2'b01)
state <= ONE_HALF;
else if(pi_money == 2'b10)
state <= TWO;
else
state <= ONE;
ONE_HALF: if(pi_money ==2'b01)
state <= TWO;
else if(pi_money == 2'b10)
state <= IDLE;
else
state <= ONE_HALF;
TWO : if((pi_money ==2'b01)||(pi_money == 2'b10))
state <= IDLE;
else
state <= TWO;
default:state <= IDLE;
endcase
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
po_cola <= 1'b0;
else if((state == ONE_HALF)&&(pi_money == 2'b0)
||(state == TWO)&&(pi_money == 2'b01)
||(state == TWO)&&(pi_money == 2'b10))
po_cola <= 1'b1;
else
po_cola <= 1'b0;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
po_money <= 1'b0;
else if((state == TWO)&&(pi_money == 2'b10))
po_money <= 1'b1;
else
po_money <= 1'b0;
endmodule